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Embedded Systems Mcqs

Q:

Which model is capable of reflecting the bidirectional transfer of information?

A) switch-level model B) gate level
C) layout model D) circuit-level model
 
Answer & Explanation Answer: A) switch-level model

Explanation: The switch model can be used in the simulation of the transistors since the transistor is the very basic component in a switch. It is capable of reflecting bidirectional transferring of the information.

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54
Q:

Which of the following can compute the exact number of clock cycles required to run an application?

A) layout model B) coarse-grained model
C) fine-grained model D) register-transaction model
 
Answer & Explanation Answer: C) fine-grained model

Explanation: The fine-grained model has the cycle-true instruction set simulation. In this modelling, it is possible to compute the exact number of clock cycles which is required to run an application.

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47
Q:

What is FMEA?

A) fast mode and effect analysis B) front mode and effect analysis
C) false mode and effect analysis D) failure mode and effect analysis
 
Answer & Explanation Answer: D) failure mode and effect analysis

Explanation: The FMEA is the failure mode and the effect analysis, in which the analysis starts at the components and tries to estimate their reliability.

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50
Q:

Which gate is used in the graphical representation, if several events cause hazard?

A) OR B) NOT
C) AND D) NAND
 
Answer & Explanation Answer: C) AND

Explanation: The fault tree analysis is done graphically by using gates. The main gates used are AND gates and OR gates. The AND gates are used in the graphical representation if several events cause hazards.

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57
Q:

Which analysis uses the graphical representation of hazards?

A) Power model B) FTA
C) FMEA D) First power model
 
Answer & Explanation Answer: B) FTA

Explanation: The FTA is done graphically by using gates mainly AND gates and OR gates. The OR gate is used to represent the single event which is hazardous.

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50
Q:

Which gate is used in the geometrical representation, if a single event causes hazards?

A) AND B) NOT
C) NAND D) OR
 
Answer & Explanation Answer: D) OR

Explanation: The fault tree analysis is done graphically by using gates mainly AND gates and OR gates. The OR gate is used to represent the single event which is hazardous. Similarly, AND gates are used in the graphical representation if several events cause hazards.

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76
Q:

What is FTA?

A) free tree analysis B) fault tree analysis
C) fault top analysis D) free top analysis
 
Answer & Explanation Answer: B) fault tree analysis

Explanation: The FTA is also known as the Fault tree analysis which is a top-down method of analyzing risks. The analysis starts with damage and comes up with the reasons for the damage. The analysis can be checked graphically by using gates.

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54
Q:

Which is a top-down method of analyzing risks?

A) FTA B) FMEA
C) Hazards D) Damages
 
Answer & Explanation Answer: A) FTA

Explanation: The FTA is Fault tree analysis which is a top-down method of analyzing risks. It starts with damage and comes up with the reasons for the damage. The analysis is done graphically by using gates.

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